High-Throughput Bilinear Pairing Processor for Server-Side FPGA Applications-Reference-Cited by-同舟云学术

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High-Throughput Bilinear Pairing Processor for Server-Side FPGA Applications

Published:2024-08 Issue:8 Volume:32 Page:1498-1511
ISSN:1063-8210
Container-title:IEEE Transactions on Very Large Scale Integration (VLSI) Systems
language:
Short-container-title:IEEE Trans. VLSI Syst.

Author:

Sakamoto Junichi¹^ORCID,Fujimoto Daisuke²^ORCID,Anzai Riku³,Yoshida Naoki¹^ORCID,Matsumoto Tsutomu¹

Affiliation:

1. Institute of Advanced Sciences, Yokohama National University, Yokohama, Japan

2. National Institute of Advanced Industrial Science and Technology, Tokyo, Japan

3. Graduate School of Environment and Information Sciences, Yokohama National University, Yokohama, Japan

Funder

Cabinet Office (CAO) through the Cross-Ministerial Strategic Innovation Promotion Program (SIP) “Cyber Physical Security for IoT Society”

JSPS KAKENHI

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Link

http://xplorestaging.ieee.org/ielx7/92/10609530/10539134.pdf?arnumber=10539134

Reference49 articles.

1. Aggregate and Verifiably Encrypted Signatures from Bilinear Maps

2. Certificateless public key encryption with keyword search

3. Faster Explicit Formulas for Computing Pairings over Ordinary Curves

4. Updating Key Size Estimations for Pairings

5. When FPGA Meets Cloud: A First Look at Performance

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