High-performance implementation of regular and easily scalable sorting networks on an FPGA-Reference-Cited by-同舟云学术

High-performance implementation of regular and easily scalable sorting networks on an FPGA

Published:2014-07 Issue:5 Volume:38 Page:470-484
ISSN:0141-9331
Container-title:Microprocessors and Microsystems
language:en
Short-container-title:Microprocessors and Microsystems

Author:

Sklyarov Valery^ORCID,Skliarova Iouliia^ORCID

Publisher

Elsevier BV

Subject

Artificial Intelligence,Computer Networks and Communications,Hardware and Architecture,Software

Reference31 articles.

1. Sorting networks on FPGAs;Mueller;Int. J. Very Large Data Bases,2012

2. J. Ortiz, D. Andrews, A configurable high-throughput linear sorter system, in: Proceedings of IEEE International Symposium on Parallel & Distributed Processing, April, 2010, pp. 1–8.

3. M. Zuluada, P. Milder, M. Puschel, Computer generation of streaming sorting networks, in: Proceedings of the 49th Design Automation Conference, San Francisco, June, 2012, pp. 1245–1253.

4. D.J. Greaves, S. Singh, Kiwi: Synthesis of FPGA circuits from parallel programs, in: Proceedings of the 16th IEEE International Symposium on Field-Programmable Custom Computing Machines – FCCM’08, USA, 2008, pp. 3–12.

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