Multipurpose Cacheing to Accelerate OpenMP Target Regions on FPGAs

Author:

Brandner Julian,Mayer Florian,Philippsen Michael

Publisher

Springer Nature Switzerland

Reference34 articles.

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3. Asano, S., Maruyama, T., Yamaguchi, Y.: Performance comparison of FPGA, GPU and CPU in image processing. In: Proceedings of the International Conference on Field Programmable Logic and Applications (FPL 2009), Prague, Czech Republic, pp. 126–131, September 2009. https://doi.org/10.1109/FPL.2009.5272532. Accessed 11 May 2023

4. Brandner, J., Mayer, F., Philippsen, M.: Reducing OpenMP to FPGA round-trip times with predictive modelling. In: Klemm, M., de Supinski, B.R., Klinkenberg, J., Neth, B. (eds.) IWOMP 2022. LNCS, vol. 13527, pp. 94–108. Springer, Cham (2022). https://doi.org/10.1007/978-3-031-15922-0_7. Accessed 11 May 2023

5. Castells-Rufas, D., et al.: Opencl-based FPGA accelerator for semi-global approximate string matching using diagonal bit-vectors. In: Proceedings of the International Conference on Field Programmable Logic and Applications (FPL 2021), Dresden, Germany, pp. 174–178, May 2021. https://doi.org/10.1109/FPL53798.2021.00036. Accessed 11 May 2023

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