Author:
Coppola Marcello,Curaba Stephane,Grammatikakis Miltos D.,Locatelli Riccardo,Maruccia Giuseppe,Papariello Francesco
Subject
Hardware and Architecture,Software
Reference53 articles.
1. STATS: a framework for microprocessor and system-level design space exploration;Albonesi;J. Syst. Architec.,1999
2. Amba Bus, Arm. Available from
3. Networks on chips: a new SoC paradigm;Benini;Computer,2002
4. Error control schemes for on-chip interconnection networks: reliability versus energy efficiency;Bertozzi,2003
5. D. Bertozzi, L. Benini, G. De Micheli, Low power error resilient for on-chip data buses, in: Proc. Design Automation, 2002, pp. 102–109
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