AdapNoC: A fast and flexible FPGA-based NoC simulator
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Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/7573873/7577295/07577377.pdf?arnumber=7577377
Cited by 20 articles. 订阅此论文施引文献 订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献
1. Controller node derivation for data distribution in Network-on-chip with ring connected binary tree topology;International Journal of Information Technology;2023-06
2. Roadmap for machine learning based network-on-chip (M/L NoC) technology and its analysis for researchers;Journal of Physics Communications;2022-02-01
3. FPGA friendly NoC simulation acceleration framework employing the hard blocks;Computing;2021-01-16
4. 3D NoC emulation model on a single FPGA;Proceedings of the Workshop on System-Level Interconnect: Problems and Pathfinding Workshop;2020-11-05
5. SRNoC: An Ultra-Fast Configurable FPGA-Based NoC Simulator Using Switch–Router Architecture;IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems;2020-10
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