FPGA friendly NoC simulation acceleration framework employing the hard blocks

Author:

Prasad B. M. PrabhuORCID,Parane Khyamling,Talawar Basavaraj

Funder

Ministry of Electronics and Information technology

Publisher

Springer Science and Business Media LLC

Subject

Computational Mathematics,Computational Theory and Mathematics,Computer Science Applications,Numerical Analysis,Theoretical Computer Science,Software

Reference31 articles.

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3. Agarwal N, Krishna T, Peh LS, Jha N (2009) GARNET: A detailed on-chip network model inside a full-system simulator. ISPASS 2009:33–42

4. Jiang N, Becker DU, Michelogiannakis G, Balfour J, Towles B, Shaw DE, Kim J, Dally WJ (2013) A detailed and flexible cycle-accurate Network-on-Chip simulator. In: 2013 IEEE international symposium on performance analysis of systems and software (ISPASS), pp 86–96

5. Kahng AB, Li B, Ls Peh (2010) ORION 2.0: a power-area simulator for interconnection networks. TVLSI XX(1):1–5

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