Transactional memories for multi-processor FPGA platforms-Reference-Cited by-同舟云学术

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Transactional memories for multi-processor FPGA platforms

Published:2011-01 Issue:1 Volume:57 Page:160-168
ISSN:1383-7621
Container-title:Journal of Systems Architecture
language:en
Short-container-title:Journal of Systems Architecture

Author:

Kachris Christoforos,Kulkarni Chidamber

Publisher

Elsevier BV

Subject

Hardware and Architecture,Software

Reference27 articles.

1. N. Njoroge, S. Wee, J. Casper, J. Burdick, Y. Teslyar, C. Kozyrakis, K. Olukotun, Building and using the ATLAS transactional memory system, in: Workshop on Architecture Research using FPGA Platforms, 12th International Symposium on High-Performance Computer Architecture, 2006.

2. B. Moyer, Packet subsystem on a chip, in: Xilinx Embedded Magazine, March 2006.

3. Transactional memory today;Herlihy;Distributed Computing and Internet Technology,2010

4. Software transactional memory;Shavit,1995

5. Hardware transactional memory: a high performance parallel programming model;Fu;Journal of Systems Architecture,2010

Cited by 3 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. High-Level Synthesis of Transactional Memory;Proceedings of the 26th Asia and South Pacific Design Automation Conference;2021-01-18

2. Hardware transactional memory architecture with adaptive version management for multi-processor FPGA platforms;Journal of Systems Architecture;2017-02

3. Adaptive Configurable Transactional Memory for Multi-processor FPGA Platforms;2015 IEEE 23rd Annual International Symposium on Field-Programmable Custom Computing Machines;2015-05

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