Hardware transactional memory: A high performance parallel programming model-Reference-Cited by-同舟云学术

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Hardware transactional memory: A high performance parallel programming model

Published:2010-08 Issue:8 Volume:56 Page:384-391
ISSN:1383-7621
Container-title:Journal of Systems Architecture
language:en
Short-container-title:Journal of Systems Architecture

Author:

Fu Chen,Wen Dongxin,Wang Xiaoqun,Yang Xiaozong

Publisher

Elsevier BV

Subject

Hardware and Architecture,Software

Reference50 articles.

1. Transactional memory: architectural support for lock-free data structures;Herlihy,1993

2. Language support for lightweight transactions;Harris,2003

3. Software Transactional Memory for dynamic-sized data structures;Herlihy,2003

4. Transactional Memory;Larus,2006

5. McRT-STM: a high performance Software Transactional Memory system for a Multi-Core runtime;Saha,2006

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1. Design-space evaluation for non-blocking synchronization in Ada: lock elision of protected objects, concurrent objects, and low-level atomics;Journal of Systems Architecture;2020-11

2. A Processing in Memory Realization Using Quantum Dot Cellular Automata (QCA): Proposal and Implementation;Journal of Nano- and Electronic Physics;2017

3. Transactional memories for multi-processor FPGA platforms;Journal of Systems Architecture;2011-01

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