Compressed tag architecture for low-power embedded cache systems

Author:

Kwak Jong Wook,Jeon Young Tae

Publisher

Elsevier BV

Subject

Hardware and Architecture,Software

Reference18 articles.

1. Computer Architecture: A Quantitative Approach, fourth ed;Patterson,2007

2. ARM Architecture Reference Model, ARM DDI 0100l, 2005.

3. Bishop Brock, Karthick Rajamani, Dynamic power management for embedded systems, in: Proceedings of the IEEE International SOC Conference, September 2003.

4. A 160-MHz, 32-b, 0.5-W CMOS RISC microprocessor;Montanaro;IEEE Journal of Solid-State Circuits,1996

5. A. Malik, B. Moyer, D. Cermak, A lower power unified cache architecture providing power and performance flexibility, in: ISLPED’00: International Symposium on Low Power Electronics and Design, 2000, pp. 241–243.

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