Layout parameter analysis in Shannon expansion theorem based on 32 bit adder circuit

Author:

Senthilpari C.,Diwakar K.,Munusamy Kumar,Francisca J. Sheela

Publisher

Elsevier BV

Subject

Metals and Alloys,Computer Networks and Communications,Fluid Flow and Transfer Processes,Hardware and Architecture,Mechanical Engineering,Biomaterials,Civil and Structural Engineering,Electronic, Optical and Magnetic Materials

Reference23 articles.

Cited by 4 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. A New Approach of an Error Detecting and Correcting Circuit by Arithmetic Logic Blocks;International Journal of Electronics and Telecommunications;2023-07-26

2. Based on FS-GDI Approach with 65 nm Technology: Low Power ALU Design;International Journal of Electronics;2022-05-16

3. A scalable high‐speed hybrid 1‐bit full adder design using XOR‐XNOR module;International Journal of Circuit Theory and Applications;2021-07-22

4. Gate Diffusion Input technique based full swing and scalable 1-bit hybrid Full Adder for high performance applications;Engineering Science and Technology, an International Journal;2020-12

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