Energy and area efficient hierarchy multiplier architecture based on Vedic mathematics and GDI logic

Author:

Shoba Mohan,Nakkeeran Rangaswamy

Funder

University Grants Commission

Publisher

Elsevier BV

Subject

Metals and Alloys,Computer Networks and Communications,Fluid Flow and Transfer Processes,Hardware and Architecture,Mechanical Engineering,Biomaterials,Civil and Structural Engineering,Electronic, Optical and Magnetic Materials

Reference30 articles.

1. Computer Arithmetic: Algorithms and Hardware Designs;Parhami,2010

2. Design, implementation and performance comparison of multiplier topologies in power-delay space;Jhamb Garima;Eng. Sci. Technol., Int. J.,2016

3. Optimized multiplier based upon 6 input LUTs and Vedic mathematics;Zakaria;World Acad. Sci. Eng. Technol.,2013

4. High level synthesis for large bit width multipliers on FPGAs: a case study;Quan,2005

5. The design and implementation of reconfigurable multiplier with high flexibility;Shi,2011

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