Design, implementation and performance comparison of multiplier topologies in power-delay space-Reference-Cited by-同舟云学术

Design, implementation and performance comparison of multiplier topologies in power-delay space

Published:2016-03 Issue:1 Volume:19 Page:355-363
ISSN:2215-0986
Container-title:Engineering Science and Technology, an International Journal
language:en
Short-container-title:Engineering Science and Technology, an International Journal

Author:

Jhamb Mansi,Garima ,Lohani Himanshu

Publisher

Elsevier BV

Subject

Metals and Alloys,Computer Networks and Communications,Fluid Flow and Transfer Processes,Hardware and Architecture,Mechanical Engineering,Biomaterials,Civil and Structural Engineering,Electronic, Optical and Magnetic Materials

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4. Optimized Carry Look-Ahead BCD Adder Using Reversible Logic: Technology Systems and Management Communications in Computer and Information Science;Tiwari,2011

5. A logic for high speed addition;Weinberger;Nat. Bureau Stand. Circulation,1958

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