Work Function Setting in High-k Metal Gate Devices
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Publisher
InTech
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http://www.intechopen.com/download/pdf/61888
Reference14 articles.
1. Shiraishi K, Akasaka Y, Umezawa N, et al. Theory of fermi level pinning of high-k dielectrics. In: Proceedings of IEEE Simulation of Semiconductor Processes and Devices, 2006 International Conference. DOI: 10.1109/SISPAD.2006.282897
2. Tseng H-H. The progress and challenges of applying high-k/metal-gated devices to advanced CMOS technologies. In: Swart JW, editor. Solid State Circuits Technologies. Rijeka: InTech; 2010. ISBN: 978-953-307-045-2. Available from: http://www.intechopen.com/books/solid-state-circuits-technologies/theprogress-and-challenges-of-applying-high-k-metal-gated-devices-to-advanced-cmos-technologies
3. Schaeffer JK, Capasso C, Fonseca LRC, et al. Challenges for the integration of metal gate electrodes. In: Proceedings of IEEE International Electron Devices Meeting. 2004. pp. 287-290. DOI: 10.1109/IEDM.2004.1419135
4. Gilmer DC, Schaeffer JK, Taylor WJ, Spencer G, Triyoso DH, Raymond M, Roan D, Smith J, Capasso C, Hegde RI, Samavedam SB, et al. In: Proceedings of 2006 European Solid-State Device Research Conference. DOI: 10.1109/ESSDER.2006.307710
5. Gilmer DC, Schaeffer JK, Taylor WJ, et al. Strained SiGe Channels for Band-Edge PMOS Threshold Voltages With Metal Gates and High-k Dielectrics in IEEE Transactions on Electron Devices. 2010;57(4):898-904. DOI: 10.1109/TED.2010.2041866
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