A 71. 4dB SNDR 30MHz BW Continuous-Time Delta-sigma Modulator Using a Time-Interleaved Noise-Shaping Quantizer in 12-nm CMOS
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Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/8766307/8777931/08777949.pdf?arnumber=8777949
Cited by 11 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献
1. Delay Error Shaping in ΔΣ Modulators Using Time-Interleaved High Resolution Quantizers;IEEE Transactions on Circuits and Systems I: Regular Papers;2023-07
2. An 81.6 dB SNDR 15.625 MHz BW Third-Order CT SDM With a True Time-Interleaving Noise-Shaping Quantizer;IEEE Journal of Solid-State Circuits;2023-04
3. An ELDC-Free 4th-Order CT SDM Facilitated by 2nd-Order NS CT-SAR and AC-Coupled Negative-R;IEEE Journal of Solid-State Circuits;2023
4. A 30-MHz BW 74.6-dB SNDR 92-dB SFDR CT ΔΣ Modulator with Active Body-Bias DAC Calibration in 22nm FDSOI CMOS;2022 IEEE Custom Integrated Circuits Conference (CICC);2022-04
5. A CT 2–2 MASH ΔΣ ADC With Multi-Rate LMS-Based Background Calibration and Input-Insensitive Quantization-Error Extraction;IEEE Journal of Solid-State Circuits;2021-10
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