First demonstration of 40-nm channel length top-gate WS2 pFET using channel area-selective CVD growth directly on SiOx/Si substrate-Reference-Cited by-同舟云学术

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First demonstration of 40-nm channel length top-gate WS2 pFET using channel area-selective CVD growth directly on SiOx/Si substrate

Published:2019-06 Issue: Volume: Page:
ISSN:
Container-title:2019 Symposium on VLSI Technology
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Author:

Cheng Chao-Ching,Chung Yun-Yan,Li Uing-Yang,Lin Chao-Ting,Li Chi-Feng,Chen Jyun-Hong,Lai Tung-Yen,Li Kai-Shin,Shieh Jia-Min,Su Sheng-Kai,Chiang Hung-Li,Chen Tzu-Chiang,Li Lain-Jong,Wong H.-S. Philip,Chien Chao-Hsin

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/8766306/8776475/08776498.pdf?arnumber=8776498

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