Advanced Fan-Out Embedded Chip Process Integration for 3D Application
Author:
Affiliation:
1. Industrial Technology Research Institute (ITRI),Electronic and Optoelectronic System Research Laboratories,Hsinchu,Taiwan,R.O.C,30010
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/10535428/10535429/10535623.pdf?arnumber=10535623
Reference5 articles.
1. Fan-out Wafer-level Packaging Process Integration for Artificial Intelligence Real Dies
2. Comparable Study for Redistribution Layers in FO POP RDL First and Last (Fan-Out Package on Package)
3. InFO (Wafer Level Integrated Fan-Out) Technology
4. Development of High Density Fan Out Wafer Level Package (HD FOWLP) with Multi-layer Fine Pitch RDL for Mobile Applications
5. Fan-Out Wafer Level Packaging Development Line;Chai;EPTC,2020
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