Fan-out Wafer-level Packaging Process Integration for Artificial Intelligence Real Dies-Reference-Cited by-同舟云学术

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Fan-out Wafer-level Packaging Process Integration for Artificial Intelligence Real Dies

Published:2023-10-25 Issue: Volume: Page:
ISSN:
Container-title:2023 18th International Microsystems, Packaging, Assembly and Circuits Technology Conference (IMPACT)
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Author:

Ouyang T. Y.¹,Xiovo O. Y.¹,Cheng R. S.¹,Chang Y. S.¹,Hung T. Y.¹,Lee C. K.¹,Lin Y. M.¹

Affiliation:

1. Industrial Technology Research Institute,Electronic and Optoelectronic System Research Laboratories,Chutung, Hsinchu,Taiwan,R.O.C.,31040

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/10348606/10348630/10348836.pdf?arnumber=10348836

Reference9 articles.

1. Thermocompression Bonding Process Design and Optimization for Warpage Mitigation of Ultra-Thin Low-CTE Package Assemblies

2. Board-Level Thermal Cycling and Drop-Test Reliability of Large, Ultrathin Glass BGA Packages for Smart Mobile Applications

3. Analysis of System-Level Reliability of Single-Chip Glass BGA Packages with Advanced Solders and Polymer Collars

4. Thermal aging reliability of socketable, surface-modified solder BGAs with and without polymer collars

5. Thermal Aging Reliability of Socketable BGA Packages With Ni–Au-Coated SAC305 Spheres

Cited by 1 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Advanced Fan-Out Embedded Chip Process Integration for 3D Application;2024 International Conference on Electronics Packaging (ICEP);2024-04-17

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