Edge termination design of a 700-V triple RESURF LDMOS with n-type top layer
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Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/7981281/7988866/07988953.pdf?arnumber=7988953
Cited by 12 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献
1. Experiments of Sub-Micron Superjunction Devices With Ultra-Low Specific On-Resistance;IEEE Electron Device Letters;2023-07
2. Ultra-high Voltage BCD Technology Integrated 1000 V 3-D Split-Superjunction devices;2022 IEEE 34th International Symposium on Power Semiconductor Devices and ICs (ISPSD);2022-05-22
3. Experiments of Homogenization Field LDMOS With Trench-Stopped Depletion;IEEE Transactions on Electron Devices;2022-05
4. Reducing the specific on-resistance for a trench-gate-integrated SOI LDMOS by using the double silicon drift layers;Results in Physics;2020-12
5. Effect of Drift Length on Shifts in 400-V SOI LDMOS Breakdown Voltage Due to TID;IEEE Transactions on Nuclear Science;2020-11
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