SleepRider: a 5.5μW/MHz Cortex-M4 MCU in 28nm FD-SOI with ULP SRAM, Biomedical AFE and Fully-Integrated Power, Clock and Back-Bias Management

Author:

Dekimpe Remi,Schramme Maxime,Lefebvre Martin,Kneip Adrian,Saeidi Roghayeh,Xhonneux Mathieu,Moreau Ludovic,Gonzalez Marco,Pirson Thibault,Bol David

Publisher

IEEE

Cited by 7 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. A RISC-V MCU with adaptive reverse body bias and ultra-low-power retention mode in 22 nm FD-SOI;2023 20th International SoC Design Conference (ISOCC);2023-10-25

2. UFBBR: A Unified Frequency and Back-Bias Regulation Unit for Ultralow-Power Microcontrollers in 28-nm FDSOI;IEEE Transactions on Circuits and Systems I: Regular Papers;2023-06

3. Post-Silicon Optimization of a Highly Programmable 64-MHz PLL Achieving 2.7-5.7 μW;2023 Design, Automation & Test in Europe Conference & Exhibition (DATE);2023-04

4. A 7T-NDR Dual-Supply 28-nm FD-SOI Ultra-Low Power SRAM With 0.23-nW/kB Sleep Retention and 0.8 pJ/32b Access at 64 MHz With Forward Back Bias;IEEE Transactions on Circuits and Systems I: Regular Papers;2023-03

5. A Sub-mW Cortex-M4 Microcontroller Design for IoT Software-Defined Radios;IEEE Open Journal of Circuits and Systems;2023

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