A RISC-V MCU with adaptive reverse body bias and ultra-low-power retention mode in 22 nm FD-SOI-Reference-Cited by-同舟云学术

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A RISC-V MCU with adaptive reverse body bias and ultra-low-power retention mode in 22 nm FD-SOI

Published:2023-10-25 Issue: Volume: Page:67-68
ISSN:
Container-title:2023 20th International SoC Design Conference (ISOCC)
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Author:

Bauer Heiner¹,Stolba Marco¹,Scholze Stefan¹,Walter Dennis¹,Mayr Christian¹,Oefelein Alexander²,Höppner Sebastian²,Scharfe André²,Schraut Flo²,Eisenreich Holger²

Affiliation:

1. TU Dresden,Electrical and Computer Engineering Dept,Dresden,Germany

2. Racyics GmbH,Dresden,Germany

Funder

Ministry of Education

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/10395912/10395932/10396509.pdf?arnumber=10396509

Reference9 articles.

1. The SpiNNaker 2 processing element architecture for hybrid digital neuromorphic computing;Höppner;arXiv:2103.08392

2. Near-Threshold RISC-V Core With DSP Extensions for Scalable IoT Endpoint Devices

3. A 0.55V 6.3uW/MHz Arm Cortex-M4 MCU with Adaptive Reverse Body Bias and Single Rail SRAM

4. Adaptive Body Bias Aware Implementation for Ultra-Low-Voltage Designs in 22FDX Technology

5. A 9-mm2 Ultra-Low-Power Highly Integrated 28-nm CMOS SoC for Internet of Things

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