UFBBR: A Unified Frequency and Back-Bias Regulation Unit for Ultralow-Power Microcontrollers in 28-nm FDSOI
Author:
Affiliation:
1. Electronic Circuit and Systems (ECS) Group, ICTEAM Institute, Université Catholique de Louvain (UCLouvain), Louvain-la-Neuve, Belgium
Funder
Fonds Européen de Développement Régional
Wallonia within the Wallonie-2020.EU Program
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Subject
Electrical and Electronic Engineering,Hardware and Architecture
Link
http://xplorestaging.ieee.org/ielx7/8919/10137339/10077772.pdf?arnumber=10077772
Reference44 articles.
1. Technology flavor selection and adaptive techniques for timing-constrained 45nm subthreshold circuits
2. Design Margin Reduction Through Completion Detection in a 28-nm Near-Threshold DSP Processor
3. A 7T-NDR Dual-Supply 28-nm FD-SOI Ultra-Low Power SRAM With 0.23-nW/kB Sleep Retention and 0.8 pJ/32b Access at 64 MHz With Forward Back Bias
4. A Bi-Directional, Zero-Latency Adaptive Clocking Circuit in a 28-nm Wide AVFS System
5. A Cortex-M3 Based MCU Featuring AVS with 34nW Static Power, 15.3pJ/inst. Active Energy, and 16% Power Variation Across Process and Temperature
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