MemPool-3D: Boosting Performance and Efficiency of Shared-L1 Memory Many-Core Clusters with 3D Integration

Author:

Cavalcante Matheus1,Agnesina Anthony2,Riedel Samuel1,Brunion Moritz3,Garcia-Ortiz Alberto3,Milojevic Dragomir4,Catthoor Francky4,Lim Sung Kyu2,Benini Luca1

Affiliation:

1. ETH Zürich,Zürich,Switzerland

2. Georgia Institute of Technology,Atlanta,Georgia,USA

3. Universität Bremen,Bremen,Germany

4. IMEC,Leuven,Belgium

Publisher

IEEE

Reference11 articles.

1. Generational changes of flip chip interconnection technology

2. Fabrication Cost Analysis and Cost-Aware Design Space Exploration for 3-D ICs

3. Macro-3D: A Physical Design Methodology for Face-to-Face-Stacked Heterogeneous 3D ICs

4. Snitch: A tiny pseudo dual-issue processor for area and energy efficient execution of floating-point intensive workloads;zaruba;IEEE Transactions on Computers,2020

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1. Impact of Pitch Scaling on 3D Die-to-Die Interconnects;2024 IEEE 74th Electronic Components and Technology Conference (ECTC);2024-05-28

2. 3D Partitioning with Pipeline Optimization for Low-Latency Memory Access in Many-Core SoCs;2024 IEEE International Symposium on Circuits and Systems (ISCAS);2024-05-19

3. Nonvolatile Memristive Materials and Physical Modeling for In‐Memory and In‐Sensor Computing;Small Science;2024-01-22

4. Impact of gate-level clustering on automated system partitioning of 3D-ICs;Microelectronics Journal;2023-09

5. Power, Performance, Area, and Cost Analysis of Face-to-Face-Bonded 3-D ICs;IEEE Transactions on Components, Packaging and Manufacturing Technology;2023-03

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