Experimental of Folded Accumulation Lateral Double-diffused Transistor with Low Specific On Resistance
Author:
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/9452126/9452187/09452249.pdf?arnumber=9452249
Cited by 6 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献
1. Design and Simulation Optimization of an Ultra-Low Specific On-Resistance LDMOS Device;IEEE Journal of the Electron Devices Society;2024
2. A Process Optimization Method of the Mini-LOCOS Field Plate Profile for Improving Electrical Characteristics of LDMOS Device;IET Circuits, Devices & Systems;2023-10-31
3. Multi-dimensional accumulation gate LDMOS with ultra-low specific on-resistance;Microelectronics Journal;2023-08
4. Analytical Model for the Surrounded Field Plate in Folded Lateral MOSFET Structure;IEEE Transactions on Electron Devices;2023-07
5. ‐asymptotically ‐periodic mild solutions for noninstantaneous impulsive integro‐differential equations with state‐dependent delay;Mathematical Methods in the Applied Sciences;2023-03-13
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