Design and Simulation Optimization of an Ultra-Low Specific On-Resistance LDMOS Device
Author:
Affiliation:
1. School of Microelectronics, South China University of Technology, Guangzhou, China
2. CanSemi Technology Inc., Guangzhou, China
Funder
Special Project for Research and Development in Key areas of Guangdong Province
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Subject
Electrical and Electronic Engineering,Electronic, Optical and Magnetic Materials,Biotechnology
Link
http://xplorestaging.ieee.org/ielx7/6245494/10416702/10332930.pdf?arnumber=10332930
Reference36 articles.
1. A Physics-Based Compact Model to Capture Cryogenic Behavior of LDMOS Transistors
2. Analysis of novel silicon based lateral power devices with floating substrate on insulator
3. Towards ultimate scaling of LDMOS with Ultralow Specific On-resistance
4. A Study of n-LDMOS Off-state Breakdown Degradation with 0.18μm BCD Technology
5. Numerical and analytical investigations for the SOI LDMOS with alternated high-k dielectric and step doped silicon pillars*
Cited by 2 articles. 订阅此论文施引文献 订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献
1. Step thickness drift region automatic design of SOI LDMOS using physics-inspired constrained simulated annealing algorithm;Microelectronics Journal;2024-11
2. A High-Performance and Low HCI Degradation LDMOS Device With a Hybrid Field Plate;IEEE Journal of the Electron Devices Society;2024
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