Timing-Driven Placement for FPGAs with Heterogeneous Architectures and Clock Constraints-Reference-Cited by-同舟云学术

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Timing-Driven Placement for FPGAs with Heterogeneous Architectures and Clock Constraints

Published:2021-02-01 Issue: Volume: Page:
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Container-title:2021 Design, Automation & Test in Europe Conference & Exhibition (DATE)
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Author:

Lin Zhifeng,Xie Yanyue,Qian Gang,Chen Jianli,Wang Sifei,Yu Jun,Chang Yao-Wen

Funder

National Key Research and Development Project

Natural Science Foundation of China

AnaGlobe

Maxeda, Synopsys, TSMC, and MOST of Taiwan

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/9473901/9473226/09474054.pdf?arnumber=9474054

Cited by 5 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. AMF-Placer 2.0: Open-Source Timing-Driven Analytical Mixed-Size Placer for Large-Scale Heterogeneous FPGA;IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems;2024-09

2. Integrating Operations Research into Very Large-Scale Integrated Circuits Placement Design: A Review;Asia-Pacific Journal of Operational Research;2024-07-06

3. Multielectrostatic FPGA Placement Considering SLICEL–SLICEM Heterogeneity, Clock Feasibility, and Timing Optimization;IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems;2024-02

4. High-performance Placement Engine for Modern Large-scale FPGAs With Heterogeneity and Clock Constraints;IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems;2023

5. High-performance placement for large-scale heterogeneous FPGAs with clock constraints;Proceedings of the 59th ACM/IEEE Design Automation Conference;2022-07-10

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