High-performance placement for large-scale heterogeneous FPGAs with clock constraints-Reference-Cited by-同舟云学术

High-performance placement for large-scale heterogeneous FPGAs with clock constraints

Published:2022-07-10 Issue: Volume: Page:
ISSN:
Container-title:Proceedings of the 59th ACM/IEEE Design Automation Conference
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Author:

Zhu Ziran¹,Mei Yangjie¹,Li Zijun²,Lin Jingwen²,Chen Jianli³,Yang Jun¹,Chang Yao-Wen⁴

Affiliation:

1. Southeast University, Nanjing, China

2. Fuzhou University, Fuzhou, China

3. Fudan University, Shanghai, China

4. National Taiwan University, Taipei, Taiwan

Publisher

ACM

Link

https://dl.acm.org/doi/pdf/10.1145/3489517.3530567

Reference14 articles.

1. Multilevel generalized force-directed method for circuit placement

2. RippleFPGA: Routability-Driven Simultaneous Packing and Placement for Modern FPGAs

3. Clock-Aware Placement for Large-Scale Heterogeneous FPGAs

4. NTUplace3: An Analytical Placer for Large-Scale Mixed-Size Designs With Preplaced Blocks and Density Constraints

5. M. R. Hestenes . Multiplier and gradient methods. Journal of optimization theory and applications, 4(5):303--320 , 1969 . M. R. Hestenes. Multiplier and gradient methods. Journal of optimization theory and applications, 4(5):303--320, 1969.

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