High-performance placement for large-scale heterogeneous FPGAs with clock constraints
Author:
Affiliation:
1. Southeast University, Nanjing, China
2. Fuzhou University, Fuzhou, China
3. Fudan University, Shanghai, China
4. National Taiwan University, Taipei, Taiwan
Publisher
ACM
Link
https://dl.acm.org/doi/pdf/10.1145/3489517.3530567
Reference14 articles.
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3. Clock-Aware Placement for Large-Scale Heterogeneous FPGAs
4. NTUplace3: An Analytical Placer for Large-Scale Mixed-Size Designs With Preplaced Blocks and Density Constraints
5. M. R. Hestenes . Multiplier and gradient methods. Journal of optimization theory and applications, 4(5):303--320 , 1969 . M. R. Hestenes. Multiplier and gradient methods. Journal of optimization theory and applications, 4(5):303--320, 1969.
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1. An effective routability-driven packing algorithm for large-scale heterogeneous FPGAs;Integration;2024-01
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