Author:
Zhang Yan ,Dong Gang ,Yang Yin-Tang ,Wang Ning ,Wang Feng-Juan ,Liu Xiao-Xian ,
Abstract
Based on the distributed interconnect power model, a novel dynamic power model is presented in this paper, in which a non-uniform interconnection structure is adopted. This model takes into account the self-heating effect and is constrained by delay, bandwidth, area, minimum interconnect width and minimum interconnect space. The validity of the proposed model is verified by 90 nm and 65 nm complementary metal-oxide semiconductor technology. The results indicate that the proposed model can cause a power consumption reduction as high as 35%, and yet the delay, area, and bandwidth are not deteriorated, when compared with the conventional power model. The proposed optimal model can be used for designing large scale interconnect router and clock network in network-on-chip structure.
Publisher
Acta Physica Sinica, Chinese Physical Society and Institute of Physics, Chinese Academy of Sciences
Subject
General Physics and Astronomy
Reference13 articles.
1. Semiconductor Industry Association 2010 International Technology Roadmap for Semiconductors 2010 (ITRS 2010)
2. Uchino T, Cong J 2002 IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst. 21 763
3. Zhu Z M, Zhong B, Yang Y T 2010 Acta Phys. Sin. 59 4895 (in Chinese) [朱樟明, 钟波, 杨银堂 2010 物理学报 59 4895]
4. Sahoo S, Data M, Kar R 2011 Proceedings of the Second International Conference on Emerging Applications of Information Technology Kolkata, India, February 19-20, 2011 p379
5. Zhou Q M, Elmore K M 2006 ACM/IEEE Design Automation Conf. San-Francisco, CA, USA, July 24-28, 2006 p965
Cited by
2 articles.
订阅此论文施引文献
订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献