Threshold Logic Technology based E-cube Routing on a 4-dimensional hypercube

Abstract

Hypercube network connection is formed by connecting different N number of nodes that are expressed as a power of 2. If each node has an address of m bits then the total number of nodes in the Hypercube network is N=2^m. In calculating the predefined routing path for the case of this E-cube network, we apply deterministic algorithm which gives a deadlock free concept. For determining predefined routing path, node addresses involved in the path are calculated by using the exclusive operation, firstly, on the node addresses of source and destination, next, on the derived nodes according to the algorithm. In the present work, the Exclusive-OR operation is performed with the help of electron-tunneling based XOR gate which is made up of Multiple input threshold logic gate. This multiple input threshold logic gate technology is really different from the existing one. By using an emerging technology we are capable of making an electronic circuit with high speed, low cost, high concentration density, light in weight, reduced gate numbers and low power consumption. This technology is relies on the condition of linear threshold logic and electron-tunneling event. When we are interested in implementing a circuit, a multi-inputs but one-output based logic-gate will be taken account of consideration. In this work, we have designed an E-cube Routing on a 4-dimensional hypercube to find out the node addresses for predefining the deadlock free routing path from source to destination. To develop this “E-cube Routing on a 4-dimensional hypercube”, we must require a specific logic called Exclusive-OR gate and for this, some small components like 2-input OR gate, 2-input AND gates of different input conditions are essential. After arranging this XOR gate in a pattern discussed in section 2, a desired circuit is implemented. All the circuit we are intended to construct are given in due places with their threshold logic and simulation set, the simulation results are provided as well. Different truth tables, derivation of threshold logic expressions are given for clear understanding. We have taken our consideration of whether the present work circuits are faster or slower than the circuits of CMOS based- and Single electron transistor (SET) based-circuits. The power consumed at the time of tunneling event for a circuit is measured and sensed that it exists in the range between 10meV to 250meV which is very small amount. All the combinational circuits we have presented in this work are of ‘generic multiple input threshold logic gate’-based.