Parallel Comparator based voltmeter using Single Electron Tunneling Transistor

Abstract

By manipulating an electron that tunnels the tunnel junction of a single electron transistor, one will be able to reach a standard output logic “1” or logic “0”. The operation of the Single Electron Transistor (SET) is depending upon the bias voltage as well as the input signal(s). By varying the input voltage levels of a SET, the output voltage levels can significantly be changed on the basis of tunneling of an electron whether tunneling happened or not. As our concentration is the measuring of an unknown voltage, we are to implement a voltmeter system to provide a digital output of 3 bits whenever an unknown input voltage is kept in touching in the input terminal. A reference/standard voltage (say 8mV) will be connected in series with eight resistances ( 8 Rs) for the purpose of making a seven threshold voltages, for 7 comparators, in an ascending order of values from ground to reference voltage for seven comparators which are used in this present work. The voltmeter implemented consists of (i) a voltage divider, (ii) a set of seven comparators, (iii) seven Exclusive-OR gates and (iv) three 4-input OR gates. The concepts of implementing “Parallel Comparator based voltmeter” is discussed in two ways (i) by classical block diagram and (ii) using Single electron transistor based circuit. The measuring of an input analog voltage will not be the same as the digital output value. A 3-bit output indicates that the input analog voltage must lie on within a particular small range of voltage. The encoder circuit which is connected to the outputs of the comparators is hard to construct whenever the three terminals output are expressed with the output variables (Wi) of the comparators. For simple and user-friendly circuit, the outputs (Wi) of the comparators are modified to Di variables so as to get the same 3-bit encoder/voltmeter output. For this purpose, 7 extra component called 2-input XORs based on SET are used. Seven such XORs are set, and the output of them are passed to three 4-input OR gates according to the required logic expressions. It is found that all the output data of the voltmeter are coherently matched with the theoretical aspects. Processing delays are found out for all circuits. Power consumptions of all of them are shown in tabular and graphical forms. All the circuit we are intending to make are provided in due places with their logic circuit or simulation set and the simulation results are provided as well. Different truth tables are given for keeping track of whether input-output relationships matches with the theoretical results. We have thought of whether the present work circuits are faster or slower than the circuits of CMOS based-circuits. The power consumed at the time of tunneling event for a circuit is measured and sensed that it exists in the range between 1×10^(-18) Joules to 22×10^(-18)Joules which is very small amount. All the combinational circuits presented in this work are of SET-based.