1. S. J. Whang K. H. Lee D. G. Shin B. Y. Kim M. S. Kim J. H. Bin J. H. Han S. J. Kim B. M. Lee Y. K. Jung S. Y. Cho C. H. Shin H. S. Yoo S. M. Choi K. Hong S. Aritome S. K. Park S. J. Hong Novel 3-dimensional dual control-gate with surrounding floating-gate (DC-SF) NAND flash cell for 1 Tb file storage application in 2010 IEEE International Electron Devices Meeting (IEDM) (IEEE 2010) pp. 29.7.1-29.7.4.
2. A 512-Gb 3-b/Cell 64-Stacked WL 3-D-NAND Flash Memory
3. Charge-trapping device structure of SiO2∕SiN∕high-k dielectric Al2O3 for high-density flash memory
4. Performance Improvement in Charge-Trap Flash Memory Using Lanthanum-Based High- $\kappa$ Blocking Oxide
5. J. Jang H.-S. Kim W. Cho H. Cho J. Kim S. I. Shim Y. Jang J. Jeong B. Son D. W. Kim K. Kim J. Shim J. S. Lim K. Kim S. Y. Yi J. Lim D. Chung H.-C. Moon S. Hwang J.-W. Lee Y.-H. Son U. Chung W.-S. Lee Vertical cell array using TCAT (Terabit Cell Array Transistor) technology for ultra high density NAND flash memory in 2009 IEEE Symposium on VLSI Technology (VLSIT) (IEEE 2009) pp. 192–193.