A Low Power 10NM FinFET design of the GRFU-Multiply Accumulate Unit for DNN Accelerators

Abstract

Abstract The paper presents a low power implementation of the GRFU based Multiply Accumulate unit for Deep Neural Network (DNN) Accelerators. The DNN is constructed based on the interconnections of many neurons. The neurons are most important structure to connect input, output and hidden layers incorporated in the DNN. The neuron has the basic operation of simultaneous addition and multiplications. The multiplication operation involves huge amount of power and area while designing an efficient neuron. Hence, the paper detailed that the RFU based MAC unit for DNN accelerators. The power reduction technique called GDI (Gate Diffusion Input) is infused with the RFUs and performance efficiency of the proposed design was validated by 10nm FinFET devices along with measuring different parameters in SPICE simulations.