An 8 Bit 12.4 TOPS/W Phase-Domain MAC Circuit for Energy-Constrained Deep Learning Accelerators-Reference-Cited by-同舟云学术

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An 8 Bit 12.4 TOPS/W Phase-Domain MAC Circuit for Energy-Constrained Deep Learning Accelerators

Published:2019-10 Issue:10 Volume:54 Page:2730-2742
ISSN:0018-9200
Container-title:IEEE Journal of Solid-State Circuits
language:
Short-container-title:IEEE J. Solid-State Circuits

Author:

Toyama Yosuke^ORCID,Yoshioka Kentaro^ORCID,Ban Koichiro,Maya Shigeru,Sai Akihide^ORCID,Onizuka Kohei

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering

Link

http://xplorestaging.ieee.org/ielx7/4/8847474/08771205.pdf?arnumber=8771205

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2. Time-Encoded Mostly Digital Feature Extraction for Voice Activity Detection Tasks;2024 IEEE International Symposium on Circuits and Systems (ISCAS);2024-05-19

3. Toward All-Digital Time-Domain Neural Network Accelerators for In-Sensor Processing Applications;2023 IEEE Nordic Circuits and Systems Conference (NorCAS);2023-10-31

4. A Low Power 10NM FinFET design of the GRFU-Multiply Accumulate Unit for DNN Accelerators;2023-08-18

5. A digitally controlled switched‐ring oscillator‐based time domain multiply‐and‐accumulate core for machine learning;International Journal of Circuit Theory and Applications;2023-07

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