Process variations and short channel effects analysis in gate-all-around nanowire field-effect transistor using a statistical Taguchi-Pareto ANOVA framework

Abstract

Abstract Gate-all-around nanowire field-effect transistor (GAA NWFET) is a viable alternative to reduce short channel effects. A 3D model of the GAA NWFET was explored by studying the effect of process parameters such as nanowire materials, gate oxide materials and high-κ coverage angles on vital transistor performance metrices specifically threshold voltage, leakage current, current ratio, subthreshold swing (SS) and drain induce barrier lowering (DIBL). It has been observed that the nanowire material of InP provides the lowest threshold voltage and highest drive current. Gate oxide material of HfO2 showed improved leakage current by 88.39%, current ratio by 1439.63%, SS by 24.16% and DIBL by 13.11% relative to the conventional NWFET with SiO2 gate oxide. Moreover, as the high-κ dielectric (HfO2) covers the gate oxide over the channel region, the gate electrostatic control over the channel region increases, thus reducing SS to an ideal value. An exhaustive Taguchi Method with Conceptual Signal-To-Noise Ratio Approach and Pareto Analysis of Variance optimization was conducted to determine the optimal design for high current ratio and low threshold voltage. This work inherently provides a framework in designing an optimized GAA NWFET by considering the device’s highest to lowest domineering design factors in affecting its performance matrices.