A Calibration Technique for DVMC with Delay Time Controllable Inverter-Reference-Cited by-同舟云学术

A Calibration Technique for DVMC with Delay Time Controllable Inverter

Published:2016 Issue:0 Volume:9 Page:30-36
ISSN:1882-6687
Container-title:IPSJ Transactions on System LSI Design Methodology
language:en
Short-container-title:IPSJ Transactions on System LSI Design Methodology

Author:

Cui Ri¹,Namba Kazuteru¹

Affiliation:

1. Graduate School of Advanced Integration Science, Chiba University

Publisher

Information Processing Society of Japan

Subject

Electrical and Electronic Engineering,Computer Science Applications

Link

https://www.jstage.jst.go.jp/article/ipsjtsldm/9/0/9_30/_pdf

Reference19 articles.

1. [1] Ahmed, N. and Tehranipoor, M.: Nanometer Technology Designs: High-Quality Delay Tests, New York (2007).

2. [2] Tanabe, T., Katoh, K., Namba, K. and Ito, H.: A Delay Measurement for VLSI Circuit by Subtraction, Trans. IEICE, Vol.J93-D, No.4, pp.460-468 (2010) (in Japanese).

3. [3] Katoh, K., Namba, K. and Ito, H.: A low-area on-chip delay measurement system using embedded delay measurement circuit, Proc. IEEE, Asian Test Symposium (ATS'10), pp.343-348 (2010).

4. [4] Pei, S., Li, H. and Li, X.: A low overhead on-chip path delay measurement circuit, Proc. IEEE, Asian Test Symposium (ATS'09), pp.145-150 (2009).

5. [5] Vercesi, L., Liscidini, A. and Castello, R.: Two-Dimensions Vernier Time-to-Digital Converter, Solid-State Circuits IEEE, Vol.45, No.8, pp.1504-1512 (2010).

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