Gate induced drain leakage reduction with analysis of gate fringing field effect on high-κ/metal gate CMOS technology
Author:
Publisher
IOP Publishing
Subject
General Physics and Astronomy,Physics and Astronomy (miscellaneous),General Engineering
Link
http://stacks.iop.org/1347-4065/54/i=6S1/a=06FG10/pdf
Reference30 articles.
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5. Integrations and challenges of novel high-k gate stacks in advanced CMOS technology
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1. Row Hammer Reduction Using a Buried Insulator in a Buried Channel Array Transistor;IEEE Transactions on Electron Devices;2022-12
2. Exploiting Fringing Fields Created by High-κ Gate Insulators to Enhance the Performance of Ultrascaled 2-D-Material-Based Transistors;IEEE Transactions on Electron Devices;2021-09
3. S-TAT Leakage Current in Partial Isolation Type Saddle-FinFET (Pi-FinFET)s;IEEE Access;2021
4. Partial Isolation Type Saddle-FinFET(Pi-FinFET) for Sub-30 nm DRAM Cell Transistors;Electronics;2018-12-21
5. Simulation Analysis in Sub-0.1 μm for Partial Isolation Field-Effect Transistors;Electronics;2018-10-02
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