Effect of test structure on electromigration characteristics in three-dimensional through silicon via stacked devices-Reference-Cited by-同舟云学术

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Effect of test structure on electromigration characteristics in three-dimensional through silicon via stacked devices

Published:2015-04-17 Issue:5S Volume:54 Page:05EE01
ISSN:0021-4922
Container-title:Japanese Journal of Applied Physics
language:
Short-container-title:Jpn. J. Appl. Phys.

Author:

Oba Yoshiyuki,De Messemaeker Joke,Tyrovouzi Anna Maria,Miyamori Yuichi,De Vos Joeri,Wang Teng,Beyer Gerald,Beyne Eric,De Wolf Ingrid,Croes Kristof

Publisher

IOP Publishing

Subject

General Physics and Astronomy,Physics and Astronomy (miscellaneous),General Engineering

Link

http://stacks.iop.org/1347-4065/54/i=5S/a=05EE01/pdf

Reference31 articles.

1. The rise of the 3rd dimension for system intergration

2. Solving Technical and Economical Barriers to the Adoption of Through-Si-Via 3D Integration Technologies

3. Challenges in the implementation of low-k dielectrics in the back-end of line

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1. Simulation on Interplay Between Morphological Evolution and Defect in Polycrystalline TSV During EM;IEEE Transactions on Electron Devices;2024-01

2. Reliability Challenges in Advanced 3D Technologies: The Case of Through Silicon Vias and SiCN–SiCN Wafer-to-Wafer Hybrid-Bonding Technologies;IEEE Transactions on Device and Materials Reliability;2023-12

3. Role of Cu/SiO₂ Rough Interface in TSV for High-Power Device Under Electromigration;IEEE Transactions on Electron Devices;2023-10

4. A Short Review of Through-Silicon via (TSV) Interconnects: Metrology and Analysis;Applied Sciences;2023-07-18

5. Electromigration in three-dimensional integrated circuits;Applied Physics Reviews;2023-05-16

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