SiC trench MOSFET with self‐biased p‐shield for low R ON‐SP and low OFF‐state oxide field

Author:

Zhang Meng1,Wei Jin2,Jiang Huaping34,Chen Kevin J.2,Cheng Ching‐Hsiang1

Affiliation:

1. Department of Industrial and Systems EngineeringThe Hong Kong Polytechnic UniversityKowloonHong Kong

2. Department of Electric and Computer EngineeringThe Hong Kong University of Science and TechnologyKowloonHong Kong

3. Dynex Semiconductor LtdLincolnLN6 3LFUK

4. Zhuzhou CRRC Times Electric Co. LtdZhuzhou412001People's Republic of China

Publisher

Institution of Engineering and Technology (IET)

Subject

Electrical and Electronic Engineering

Cited by 12 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. Enhanced gate biasing resilience in asymmetric and double trench SiC MOSFETs towards generalized highly reliable power electronics;Microelectronics Reliability;2024-03

2. Characterization, Analysis, and Failure Investigation of SiC Materials and Power Devices;2023 20th China International Forum on Solid State Lighting & 2023 9th International Forum on Wide Bandgap Semiconductors (SSLCHINA: IFWS);2023-11-27

3. SiC Trench MOSFET with Depletion-Mode pMOS for Enhanced Short-Circuit Capability and Switching Performance;Electronics;2023-11-24

4. A Double Trench SiC Power MOSFET with Integrated Freewheeling Heterojunction Diode for Improved Third Quadrant Performance;2022 IEEE 16th International Conference on Solid-State & Integrated Circuit Technology (ICSICT);2022-10-25

5. Analysis of 1st & 3rd Quadrant Electrothermal Robustness of Symmetrical and Asymmetrical Double- Trench SiC Power MOSFETs Under UIS;2022 IEEE Workshop on Wide Bandgap Power Devices and Applications in Europe (WiPDA Europe);2022-09-18

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