Evaluation of static noise margin of 6T SRAM cell using SiGe/SiC asymmetric dual‐ k spacer FinFETs

Author:

Gopal Maisagalla1,Sharma Vishal1,Vishvakarma Santosh K.1

Affiliation:

1. Discipline of Electrical EngineeringIndian Institute of TechnologyIndoreIndia

Publisher

Institution of Engineering and Technology (IET)

Subject

Condensed Matter Physics,General Materials Science,Biomedical Engineering,Bioengineering

Reference20 articles.

1. Ultrathin-body SOI MOSFET for deep-sub-tenth micron era

2. CollaertN.KeersgieterA.D.DixitA.et al.: ‘Multi‐gate devices for the 32 nm technology node and beyond’.Proc. 37th ESSDERC 11–13 September2007 pp.143–146

3. Device-Circuit Analysis of Double-Gate MOSFETs and Schottky-Barrier FETs: A Comparison Study for Sub-10-nm Technologies

4. BalasubramanianS.ChangL.NikolicB.et al.: ‘Circuit performance implications for double‐gate MOSFET scaling below 25 nm’.Proc. Silicon Nanoelectronics Workshop 2003 pp.16–17

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