Match‐line control unit for power and delay reduction in hybrid CAM-Reference-Cited by-同舟云学术

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Match‐line control unit for power and delay reduction in hybrid CAM

Published:2021-02-21 Issue:3 Volume:15 Page:272-283
ISSN:1751-858X
Container-title:IET Circuits, Devices & Systems
language:en
Short-container-title:IET Circuits, Devices & Systems

Author:

Hussain Sheikh Wasmir¹^ORCID,Mahendra Telajala Venkata²^ORCID,Mishra Sandeep³^ORCID,Dandapat Anup¹^ORCID

Affiliation:

1. Department of Electronics and Communication Engineering National Institute of Technology Meghalaya Shillong Meghalaya India

2. School of Electronics Engineering,Vellore Institute of Technology‐Andhra Pradesh University Amaravati Andhra Pradesh India

3. Department of Electronics and Communication Engineering Indian Institute of Information Technology Pune Pune Maharashtra India

Publisher

Institution of Engineering and Technology (IET)

Subject

Electrical and Electronic Engineering,Control and Systems Engineering

Link

https://onlinelibrary.wiley.com/doi/pdf/10.1049/cds2.12024

Reference28 articles.

1. A 28 nm Configurable Memory (TCAM/BCAM/SRAM) Using Push-Rule 6T Bit Cell Enabling Logic-in-Memory

2. Content-Addressable Memory (CAM) Circuits and Architectures: A Tutorial and Survey

3. Emerging Trends in Design and Applications of Memory-Based Computing and Content-Addressable Memories

4. A 65 nm 0.165 fJ/Bit/Search 256$\,\times\,$144 TCAM Macro Design for IPv6 Lookup Tables

5. A CAM with mixed serial-parallel comparison for use in low energy caches

Cited by 2 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Low power content addressable memory using common match line scheme for high performance processors;Analog Integrated Circuits and Signal Processing;2024-08-03

2. FASTA: Revisiting Fully Associative Memories in Computer Microarchitecture;IEEE Access;2024

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