FASTA: Revisiting Fully Associative Memories in Computer Microarchitecture
Author:
Affiliation:
1. Department of Computer Engineering, Modeling, Electronics and Systems, University of Calabria, Arcavacata di Rende, Italy
2. EnICS Labs, Faculty of Engineering, Bar-Ilan University, Ramat Gan, Israel
Funder
HORIZON EUROPE Framework Programme
Ministero dell?Istruzione, dell?Universit? e della Ricerca
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Link
http://xplorestaging.ieee.org/ielx7/6287639/10380310/10409164.pdf?arnumber=10409164
Reference103 articles.
1. A survey of microarchitectural timing attacks and countermeasures on contemporary hardware
2. Disaggregated Memory in the Datacenter: A Survey
3. Protection of Associative Memories Using Combined Tag and Data Parity (CTDP)
4. BP-SCIM: A Reconfigurable 8T SRAM Macro for Bit-Parallel Searching and Computing In-Memory
5. Efficient virtual memory for big memory servers
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