Low power architecture for floating point MAC fusion-Reference-Cited by-同舟云学术

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Low power architecture for floating point MAC fusion

Published:2000 Issue:4 Volume:147 Page:288
ISSN:1350-2387
Container-title:IEE Proceedings - Computers and Digital Techniques
language:en
Short-container-title:IEE Proc., Comput. Digit. Tech.

Author:

Pillai R.V.K.,Al-Khalili D.,Al-Khalili A.J.

Publisher

Institution of Engineering and Technology (IET)

Subject

Computational Theory and Mathematics,Hardware and Architecture,Theoretical Computer Science

Link

https://digital-library.theiet.org/content/journals/10.1049/ip-cdt_20000481?crawler=true&mimetype=application/pdf

Reference22 articles.

1. Second-generation RISC floating point with multiply-add fused

2. Leading-zero anticipatory logic for high-speed floating point addition

Cited by 6 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. An Evolutionary Normalization Algorithm for Signed Floating-Point Multiply-Accumulate Operation;Computers, Materials & Continua;2022

2. Comparative Review of MAC Architectures;Soft Computing for Intelligent Systems;2021

3. Low-latency VLSI architecture of a 3-input floating-point adder;APCCAS 2008 - 2008 IEEE Asia Pacific Conference on Circuits and Systems;2008-11

4. Configurable VLSI architecture of a 3-input floating-point adder;2008 International Conference on Signals and Electronic Systems;2008

5. Architectural design of a fast floating-point multiplication-add fused unit using signed-digit addition;IEE Proceedings - Computers and Digital Techniques;2002

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