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Finite state machine encoding for VHDL synthesis

  • Published:2001-01-01 Issue:1 Volume:148 Page:23-30
  • ISSN:1350-2387
  • Container-title:IEE Proceedings - Computers and Digital Techniques
  • language:en
  • Short-container-title:

Author:

Kuusilinna K.,Hämäläinen T.,Saarinen J.,Lahtinen V.

Publisher

Institution of Engineering and Technology (IET)

Subject

Computational Theory and Mathematics,Hardware and Architecture,Theoretical Computer Science

Reference27 articles.

1. ANSI∕IEEE STD 1076–1993: `IEEE standard VHDL language reference manual' (IEEE, Piscataway, NJ, l994)

2. KURUP, P., and ABBASI, T.: ‘Logic synthesis using synopsys®’, (Kluwer, Boston, MA 1995)

3. Optimizing interacting finite state machines using sequential don't cares

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