1. Miyazaki, N., Nakada, H., Tsutsui, A., Yamada, K., Ohta, N.: Performance improvement technique for synchronous circuits realized as LUT-Based FPGA’s. IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 3(3), 455–459 (1995)
2. Jozwiak, L., Slusarczyk, A., Chojnacki, A.: Fast and compact sequential circuits through the information-driven circuit synthesis. In: Proceedings of the Euromicro Symposium on Digital Systems Design, Warsaw, Poland, 4–6 September 2001, pp. 46–53 (2001)
3. Huang, S.-Y.: On speeding up extended finite state machines using catalyst circuitry. In: Proceedings of the Asia and South Pacific Design Automation Conference (ASAP-DAC), Yokohama, January-February, 2001, pp. 583–588 (2001)
4. Kuusilinna, K., Lahtinen, V., Hamalainen, T., Saarinen, J.: Finite state machine encoding for VHDL synthesis. Comput. Dig. Techniques, IEE Proc. 148(1), 23–30 (2001)
5. Rafla, N.I., Davis, B.A.: Study of finite state machine coding styles for implementation in FPGAs. In: Proceedings of the 49th IEEE International Midwest Symposium on Circuits and Systems, San Juan, USA, 6–9 August 2006, vol. 1, pp. 337–341 (2006)