AS8‐static random access memory (SRAM): asymmetric SRAM architecture for soft error hardening enhancement
Author:
Affiliation:
1. LAMIHUniversity of ValenciennesFrance
2. IRT RaileniumFrance
3. CECSUniversity of CaliforniaIrvineUSA
Publisher
Institution of Engineering and Technology (IET)
Subject
Electrical and Electronic Engineering,Control and Systems Engineering
Link
https://onlinelibrary.wiley.com/doi/pdf/10.1049/iet-cds.2015.0318
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4. Error Detection in Majority Logic Decoding of Euclidean Geometry Low Density Parity Check (EG-LDPC) Codes
5. Guena P.: ‘A cache primer’ Application Note Freescale Semiconductors 2004
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