Digital calibration technique using a signed counter for charge pump mismatch in phase‐locked loops-Reference-Cited by-同舟云学术

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Digital calibration technique using a signed counter for charge pump mismatch in phase‐locked loops

Published:2013-11 Issue:6 Volume:7 Page:313-318
ISSN:1751-858X
Container-title:IET Circuits, Devices & Systems
language:en
Short-container-title:IET Circuits, Devices & Systems

Author:

Jeong Chan‐Hui¹,Kim Kyu‐Young²,Kwon Chan‐Keun¹,Kim Hoonki³,Kim Soo‐Won³

Affiliation:

1. Department of Nano Semiconductor EngineeringKorea University1, 5‐ka, Anam‐dongSeongbuk‐guSeoul136‐713Republic of Korea

2. SK Hynix Semiconductor Inc.Icheon, Seongbuk‐guGyeongggi‐do467‐701Republic of Korea

3. Department of Electrical EngineeringKorea University1, 5‐ka, Anam‐dongSeongbuk‐guSeoul136‐713Republic of Korea

Funder

Ministry of Education, Science and Technology

Publisher

Institution of Engineering and Technology (IET)

Subject

Electrical and Electronic Engineering,Control and Systems Engineering

Link

https://onlinelibrary.wiley.com/doi/pdf/10.1049/iet-cds.2013.0011

Reference21 articles.

1. Allen A. Desai J. Verdico F. Anderson F. Mulvihill D. Krueger D.: ‘Dynamic frequency‐switching clock system on a quad‐core Itanium@processor’.Proc. Int. Solid‐State Circuits Conf. 2009 pp.77–80

2. Rylyakov A. Tierno J. Ainspan H. et al.: ‘Bang‐bang digital PLLs at 11 and 20 GHz with sub‐200 fs integrated jitter for high‐speed serial communication application’.Proc. Int. Solid‐State Circuits Conf. 2009 pp.94–96

3. Mismatch Shaping Techniques to Linearize Charge Pump Errors in Fractional-$N$ PLLs

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