1. [1] J.-S. Lee, et al.: “Charge pump with perfect current matching characteristics in phase-locked loops,” Electronics Letters 36 (2000) 1907 (DOI: 10.1049/el:20001358).
2. [2] C.-M. Hung and K.K. O: “A fully integrated 1.5-V 5.5-GHz CMOS phase-locked loop,” IEEE J. Solid-State Circuits 37 (2002) 521 (DOI: 10.1109/4.991390).
3. [3] S.M. Schober, et al.: “A charge transfer-based high performance, ultra-low power CMOS charge pump for PLLs,” Analog Integrated Circuits and Signal Processing 89 (2016) 561 (DOI: 10.1007/s10470-016-0829-7).
4. [4] I.-C. Hwang and S.-G. Bae: “Low-glitch, high-speed charge-pump circuit for spur minimization,” Electronics Letters 45 (2009) 1273 (DOI: 10.1049/el.2009.2660).
5. [5] Z. Zhang, et al.: “Source-switched charge pump with reverse leakage compensation technique for spur reduction of wideband PLL,” Electronics Letters 52 (2016) 1211 (DOI: 10.1049/el.2016.1036).