Low‐jitter DLL applied for two‐segment TDC
Author:
Affiliation:
1. Wuxi Branch SchoolSoutheast UniversityWuxi214135People's Republic of China
2. School of MicroelectronicsSoutheast UniversityNanjing210096People's Republic of China
Funder
National Key Research and Development Program of China
Publisher
Institution of Engineering and Technology (IET)
Subject
Electrical and Electronic Engineering,Control and Systems Engineering
Link
https://onlinelibrary.wiley.com/doi/pdf/10.1049/iet-cds.2016.0342
Reference21 articles.
1. Precise Multiphase Clock Generation Using Low-Jitter Delay-Locked Loop Techniques for Positron Emission Tomography Imaging
2. A High-Linearity, 17 ps Precision Time-to-Digital Converter Based on a Single-Stage Vernier Delay Loop Fine Interpolation
3. A 9 b, 1.25 ps Resolution Coarse–Fine Time-to-Digital Converter in 90 nm CMOS that Amplifies a Time Residue
4. Synchronization in a Multilevel CMOS Time-to-Digital Converter
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