A Digital Uncertainty-Tolerant Mismatch Compensation Method in a 17-channel Counter-Sampling Based TDC Architecture-Reference-Cited by-同舟云学术

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A Digital Uncertainty-Tolerant Mismatch Compensation Method in a 17-channel Counter-Sampling Based TDC Architecture

Published:2021-10-29 Issue: Volume: Page:
ISSN:
Container-title:2021 IEEE 3rd International Conference on Circuits and Systems (ICCS)
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Author:

Yang Jie¹,Zhao Ye²,Zhao Jie¹

Affiliation:

1. University of Chinese Academy of Sciences,Institute of Microelectronics, Chinese Academy of Sciences,Key Lab. Of Silicon Device and Technology,Beijing,China

2. Chinese Academy of Sciences,Institute of Microelectronics,Key Lab. Of Silicon Device and Technology,Beijing,China

Funder

Research and Development

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/9697107/9697111/09697126.pdf?arnumber=9697126

Reference21 articles.

1. Synchronization in a Multilevel CMOS Time-to-Digital Converter

2. A 100-m Range 10-Frame/s 340$\,\times\, $96-Pixel Time-of-Flight Depth Sensor in 0.18-$\mu\hbox{m}$ CMOS

3. A LIDAR sensor prototype with embedded 14-bit 52 ps resolution ILO-TDC array

4. A 15ps resolution time-to-digital converter with on-chip PLL counting for LiDAR multi-object sensors

5. A Time-to-Digital Converter Based on a Multiphase Reference Clock and a Binary Counter With a Novel Sampling Error Corrector

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