A High-precision Delay Locked Loop with Current Mismatch Calibration in 40nm CMOS
Author:
Affiliation:
1. Tsinghua University,Shenzhen International Graduate School,Shenzhen,China
2. ESAT-MICAS KU Leuven,Department of Elektrotechniek,Leuven,Belgium
Funder
National Natural Science Foundation of China
Chongqing Science and Technology Commission
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/10210847/10211258/10211994.pdf?arnumber=10211994
Reference7 articles.
1. Low-Phase-Error Small-Area 4-Phase DLL With a Single-Ended-Differential-Single-Ended Voltage-Controlled Delay Line
2. Charge-pump reducing current mismatch in DLLs and PLLs;ha;2006 IEEE International Symposium on Circuits and Systems (ISCAS),2006
3. Static Phase Offset Reduction Technique for Delay Locked Loops
4. A High Phase Accuracy Multiphase DLL with Optimized VCDL Structure
5. Auto-Zeroing Static Phase Offset in DLLs Using a Digitally Programmable Sensing Circuit
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