Closed‐form impedance model for annular through‐silicon via pairs in three‐dimensional integration-Reference-Cited by-同舟云学术

Closed‐form impedance model for annular through‐silicon via pairs in three‐dimensional integration

Published:2015-06 Issue:8 Volume:9 Page:808-813
ISSN:1751-8733
Container-title:IET Microwaves, Antennas & Propagation
language:en
Short-container-title:IET Microwaves, Antennas & Propagation

Author:

Chen Aobo¹,Liang Feng¹,Wang Gaofeng²,Wang Bing‐Zhong¹

Affiliation:

1. Institute of Applied Physics, School of Physical ElectronicsUniversity of Electronic Science and Technology of ChinaChengdu610054People's Republic of China

2. Key Laboratory of RF Circuits and Systems of the Ministry of EducationHangzhou Dianzi UniversityZhejiang310018People's Republic of China

Funder

National Natural Science Foundation of China

China Postdoctoral Science Foundation

Fundamental Research Funds for the Central Universities

Publisher

Institution of Engineering and Technology (IET)

Subject

Electrical and Electronic Engineering

Link

https://onlinelibrary.wiley.com/doi/pdf/10.1049/iet-map.2014.0606

Reference21 articles.

1. 3-D ICs: a novel chip design for improving deep-submicrometer interconnect performance and systems-on-chip integration

2. Introduction to Three-Dimensional Integration

3. Closed-Form Expressions of 3-D Via Resistance, Inductance, and Capacitance

4. Electrical Modeling and Characterization of Through Silicon via for Three-Dimensional ICs

5. Compact AC Modeling and Performance Analysis of Through-Silicon Vias in 3-D ICs

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